RTL Engineer (Power Analysis)

La Fosse is looking for an RTL Engineer who will join a highly focused group where they analyse and optimise the power of their next generation compute solutions using innovative technologies, methodologies and tools.

You will:

• Analyse the power efficiency of SoC design features from early estimation to final product validation.
• Developing and running RTL simulator and emulator based workloads to analyse the power of the hardware design.
• Taking pre-silicon design power measurements throughout the SoC development cycle from early modelling, RTL analysis, to in-depth timing annotated netlist analysis.
• Analysis engineers collaborate with multiple teams from SoC Architecture, Performance Analysis, Microarchitecture Design, to Physical design to develop and analyse real software use-cases and the physical hardware.
• Building relevant metrics along with visualisation to demonstrate the hardware power signature and capabilities of the compute subsystems.
• Reviewing the quality and accuracy of data produced by the latest EDA power analysis tool flows.
• Continuously innovating by improving the power analysis methodologies used by the team.

Required Skills and Experience :
We are seeking experienced engineers for a multi-disciplinary role in power analysis. Ideal candidates have past experience in power analysis or are motivated engineers with valuable transferable skills from design, implementation, or verification backgrounds.

• Skilled in performing power modelling or pre-silicon power analysis flows.
• Experience with low power design features and techniques, including clock and power gating, voltage/frequency scaling, memory/logic retention.
• Ability to understand and balance trade-offs between power, performance, and area.
• Familiar with developing RTL using Verilog, System Verilog, or VHDL.
• Knowledge of Physical Implementation flow from RTL through Synthesis, Place & Route to STA.

“Nice To Have” Skills and Experience :

• A background in development based processors based SoC system designs.
• Development or analysis of CPU or Graphics benchmarks for PPA analysis.
• Experience using tools for power analysis, power delivery and signoff. (e.g. PowerPro, PrimePower, Redhawk, etc)
• Background in running simulation/emulation tools. (e.g. VCS, Questasim, Incisive, Veloce Strato, Palladium, Zebu, etc)
• Good understanding of the concepts and tools related to synthesis, place & route, clock tree synthesis, constraint development, timing closure. (e.g. Innovus, Tempus, etc)